Lawrence Berkeley National Laboratory Background
Currently, data centers are bigger than football fields and require massive amounts of energy to operate. Yet large scale computing needs in science, industry, and for national security continue to push computing beyond its current capacity.
The emergence of rapid single flux quantum (RSFQ) superconducting logic offers a new design methodology and computational model that could reap orders of magnitude higher performance for the same power. Unfortunately, while there have been tremendous advances in both the theory and practice of superconducting logic over the years, significant engineering challenges continue to limit the computational potential of this approach. In contrast to semiconductor logic, where logic cells are combinational and their output is a pure function of the levels of all the inputs present at any time, the majority of Single Flux Quantum (SFQ) logic gates are sequential and operate on pulses rather than levels. Because pulses travel ballistically rather than diffusively through a channel, once they have tran- sited there is no “record” of their value that can be used in downstream computations. Implementing a chain of Boolean operations (e.g. an OR or ANDs) thus requires the very careful layout and synchronization of timing along each and every path with picosecond-level precision.
Researchers at UC Santa Barbara, NIST Labs, and Berkeley Laboratory have designed temporal logic computation primitives in rapid single flux quantum (RSFQ) superconducting logic, bringing together three different areas of work – superconducting logic, temporal predicate logic, and delay-based codes. With this design, they have invented a new data-driven-self timed scheme (DDST) to remove the majority of clock distribution overhead found in traditional RSFQ logic cells.
Circuit innovations were applied in order to make operators function and make some of them stateful. Compared to traditional methods that use Single Flux Quantum (SFQ) cells to construct Boolean gates, the scientists used basic RSFQ cells for the realization of the temporal gates that can maintain state in order to record the arrival of SFQ pulses in certain time windows. Unlike traditional Boolean RSFQ gates, the operators of this work can be asynchronous or self-clocked without additional overhead. The latter feature allowed the clock to be transmitted alongside with data in order to pass timing information without requiring expensive clock trees or other synchronization overheads.
To validate their hypothesis, the scientists implemented three temporal kernels in RSFQ and compared their performance against their CMOS counterparts, showing more than an order of magnitude improvements.
Stage of Development
The disruptive technology represented by RSFQ results in increased processing capability as well as data and computation complexity expansion. It can condense massive data centers and high performance computing (HPC) systems into large room-sized systems with the same power. RSFQ can also provide major energy savings as it promises order of magnitude improvements in computational power for less energy consumed. This invention:
Allows expression of delay-based computations
Increases computational and processing speed and capability
Increases energy efficiency of computation
Massively reduces the technical footprint size of data centers
Next-generation data centers and high performance computing (HPC) systems
Large-scale science computing
National security computing
Available for licensing or collaborative research.