C2018-05 – Chip Warpage Reduction via Raised Free Bending Geometries

Technology # 18-05 A method for Chip Warpage Reduction A key challenge in microelectronic assembly arises when chip warpage, resulting from thermal expansion mismatch in layered materials, drives incompatibility in assembly, and can result in interfacial stresses when experiencing temperature swings native to device operation. Currently linear copper structures are used to deliver current and signals to and from the active elements in the device. The layout and direction of these are directly related to the warpage that is demonstrated and often have to be balanced in the design in attempt to homogenize the warpage. This invention/technology is available for licensing. For interested parties seeking further information, feel free to contact: Mark Allen Lanoue Technology Manager / Tech Ventures University of Arkansas (479) 575-7243 malanoue@uark.edu Technology Ventures ventures@uark.edu 479-575-7243

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