C2018-31 – On-Chip IEC ESD Protection Using Parasitic PNP Devices

Technology #18-31 The invention proposes a novel area-efficient rail-based ESD protection structure High speed interface ICs require both IC-level and system level ESD protections due to system exposure to static electricity discharges. On-chip ESD protections for high speed interface ICs are difficult due to the stringent pin requirements. Specifically, the ESD designs for system-level ESD requirements are more challenging because of the high discharge current, limited type of ESD components and narrow protection window. Although system-level stress that reaches ICs will vary according to the board-level components and PCB layout, on-chip IEC ESD protection structure typically requires a tremendous amount of chip area. Therefore, area efficient IEC ESD and low-capacitance HBM ESD protections for high-speed interface ICS are highly desire to improve the robustness and reliability of the circuit design. Technology Ventures ventures@uark.edu 479-575-7243

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