High-Gain CMOS Inverter at Low Vdd Down to 0.5 V Consisting of WSe2 n/p FETs

Achieved high gain of 9 at Vdd = 0.5 V in WSe2 CMOS inverter by developing appropriate doping technique and gate stack technology Open Innovation Platform Tokyo Tech admin@oi-p.titech.ac.jp 0459245180

February 14, 2022

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High-Gain CMOS Inverter at Low Vdd Down to 0.5 V Consisting of WSe2 n/p FETs

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