Multiple Address Decoders for Memory Systems to Improve Performance and to Thwart Cyber Attacks

University of North Texas Technology Overview
The invention is a computer system cache decoder which randomizes the cache memory locations where the data is stored for high performance. 
In this invention, the researchers used different portions of an object for “set index” instead of the same lower end bits as used in today’s processors. In fact, the researchers will use different address bits as set index for different objects, or for different applications. The use of different address bits for set index will spread objects across cache memories, leading to more uniform utilization of cache memory entries.
In addition, this will also thwart some cybersecurity attacks aimed at discovering secret keys; such attacks rely on the fact that cache memories always use the same lower bits of object’s address to locate data. Computer control software (such as operating systems, compilers, and application run-time systems) can randomly select different address bits to form a set-index. It is not necessary to choose consecutive bits for set-index, unlike the current methods used for addressing memory systems making this invention a superior and efficient technology compared to other decoders today. 
A physical cache memory that is divided into one or more virtual segments using multiple circuits to decode addresses is provided. An address mapping and an address decoder isselected for each virtual segment. The address mapping comprises two or more address bits as set indexes for the virtual segment and the selected address bits are different for each virtual segment. A cache address decoder is provided for each virtual segment to enhance execution performance of programs or to protect against the side channel attack. Bach physical cache address decoder comprises an address mask register to extract the selected address bits to locate objects in the virtual segment. The foregoing can be implemented as a method or apparatus for protecting against a side channel attack. 
Computer memory systems in general, and cache memories in particular use a selected portion of an object address to locate the object in the memory. Typically address bits from the lower end of the object address are used for this purpose and these bits collectively are known as the “set-index”; these bits are used as an index into the cache memory to locate one or more memory locations (collectively called a cache set).
Then, the “tag” bits stored at these locations are compared with the remaining portion of the object address to verify that at least one of the data items currently stored in the identified set of cache memory locations is the object being sought. A cache miss results if none of the tag bits of the locations in the cache set match the address “tag” bits of the object. Then higher-level memories (including higher level caches and DRAM “main” memories) are consulted to obtain the missing object.
Benefits
To sum up a few competitive benefits that the technology holds over competing cache encryption technologies are:

Safeguards critical data (e.g., DES/AES encryption keys) against all known cache memory attacks using a general solution.
Provides higher utilization of the cache memory than fixed partition based approaches.
Simpler hardware design than permutation table-based cache address decoders.
Higher performance compared to cache locking approaches.

Applications
Since microprocessors are so pervasive and are expanding into more and more products, and because security is becoming increasingly important, there is clearly a need for technologies that increase the security of processor memory accesses and the multiple cache address decoders have significant advantages over the many competing solutions. 
The multiple cache decoder innovation has advantages over existing side channel attack Solutions. Moreover, there is a large and growing market for microprocessor-based security.
IT security industries, computing industry and the computer hardware sector are top potential markets for this invention.

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